The present invention relates to a process for manufacturing a semiconductor device. More specifically, the present invention relates to a technique for suppressing etching damage at the time of formation of a wiring pattern using a dry etching method.
In a manufacturing process of a semiconductor device, field effect transistors are formed on a semiconductor substrate and thereafter a wiring process step for wiring these field effect transistors is performed.
In the present wiring process step, an insulating film is first deposited on the semiconductor substrate and a contact hole is formed in place with respect to the insulating film. Subsequently, a metal material for wiring is deposited within the contact hole and on the insulating film. Then, a metal material layer provided on the insulating film is patterned to thereby complete a wiring pattern. When a two-layer wiring is made, a second insulating film is further deposited on the insulating film, a through hole is defined therein, and a metal material is deposited thereon, and a metal material layer provided on the insulating film is patterned.
In general, a photolithography process is used for the patterning of the metal material layer. In the photolithography process, a resist film is applied onto the metal material layer and exposed in alignment with a wiring pattern to be formed. Thereafter, an exposure region or a non-exposure region of the resist film is removed, thereby forming a resist pattern. Then, the metal material layer is subjected to etching processing with the resist pattern as a mask, whereby a desired wiring pattern is obtained.
An etching processing technology is broadly divided into wet etching and dry etching (plasma etching or the like). The dry etching is inferior to the wet etching in that it is high in cost, whereas the dry etching is superior to the wet etching in that high-precision processing is enabled. Therefore, when a semiconductor device high in integration degree is manufactured, each wiring pattern is often formed using a dry etching technology.
However, the following drawbacks arise where each wiring pattern is formed using the dry etching technology.
When the wiring pattern is formed by the dry etching, an electric charge developed by the dry etching reaches a gate electrode through the inside of a contact hole and a lower wiring pattern and is stored in a gate insulating film. This storage of electric charge results in etching damage. The etching damage yields degradation in the characteristic of a field effect transistor, such as a variation in threshold voltage.
As a technique for suppressing the storage of an electric charge by dry etching, there has been known one described in, for example, a patent document 1 (Japanese Unexamined Patent Publication No. 2003-282570). In the present technique, a contact hole for making a floating conductive layer conductive to a semiconductor substrate is provided in a non-shot area (i.e., an area in which an integrated circuit pattern is not transferred in an exposure process) of a semiconductor wafer to thereby suppress the storage of the electric charge into the conductive layer (refer to, for example, FIG. 2 of the patent document 1).
In order to prevent the above-described storage of electric charge into the gate insulating film through the use of the technique described in the patent document 1, a contact hole for connecting a metal material layer for a wiring pattern and its corresponding semiconductor substrate may be formed.
However, the technique of the patent document 1 is accompanied by drawbacks that since the contact hole for discharging the stored electric charge is formed in the non-shot area, there is a need to add the exposure process and correspondingly the number of process steps increases, thus raising the cost of manufacturing.
On the other hand, since such a contact hole must be formed one by one or plural by plural for every wiring pattern, an increase in circuit scale becomes innegligible where an attempt is made to provide these contact holes in a device area (an area lying within a shot area, in which a semiconductor integrated circuit is formed). Thus, this results in trouble in terms of attainment of a reduction in chip area.